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6.3
DPM Command/Response Summary
Table 20 provides a summary of SPI commands and responses.
Table 20. SPI Command/Response Summary
Command
Pin
D15 D14 D13 D12 D11 D10 D9
Bit
D8 D7
D6
D5
D4
D3
D2
D1
D0
SPI DPM Entry
Register Pointer Write
Register Pointer Read
Register Data Write
Register Data Read
Acceleration Data Read
D IN
D OUT
D IN
D OUT
D IN
D OUT
D IN
D OUT
D IN
D OUT
D IN
D OUT
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
0
1
0
0
0
0
1
0
1
1
P
P=0
P
0
P
P=1
P
P=1
P
1
0
P
0
0
0
P
1
0
1
0
D9
1
0
X
1
X
1
X
0
X
0
0
D8
0
1
A7
0
X
A7
D7
A7
X
D7
0
D7
1
0
A6
0
X
A6
D6
A6
X
D6
0
D6
0
1
A5
0
X
A5
D5
A5
X
D5
0
D5
1
0
A4
0
X
A4
D4
A4
X
D4
0
D4
1
0
A3
0
X
A3
D3
A3
X
D3
0
D3
1
0
A2
0
X
A2
D2
A2
X
D2
0
D2
0
1
A1
0
X
A1
D1
A1
X
D1
0
D1
0
1
A0
0
X
A0
D0
A0
X
D0
0
D0
D IN
0
0
D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D OUT
1
No Response (all 0s) - DPM Entry Locked Out
D IN
0
1
1
D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Invalid Command Response
D OUT
1
No Response (all 0s) - DPM Entry Locked Out
(Waiting for SPI DPM Entry)
D IN
1
1
D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D OUT
0
0
No Response (all 0s) - DPM Entry Locked Out
D IN
D OUT
1
0
0
1
D[13] D[12] D[11]
D[13] D[12] D[11]
...
...
D[x]
D[x]
Not SPI DPM Entry Command
No Response (all 0s) - DPM Entry Locked Out
Invalid Command Response
D IN X X X X X X X
D OUT d[15] d[14] d[13] d[12] d[11] d[10] d[9]
X
d[8]
X
d[7]
X
d[6]
X
d[5]
X
d[4]
X
d[3]
X
d[2]
X
d[1]
X
d[0]
Parity Fault Response
(Subsequent Message Response)
D IN
D OUT
X
1
X
0
X
0
X
0
X
0
X
0
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
6.4
Register Pointer Operations
Access to internal registers is accomplished via a pointer register. The pointer contains the address of the register affected by
register data write and read operations. Two register pointer operations are provided: Register Pointer Write, and Register Pointer
Read. Command and response information is shown in Table 20 .
6.5
Register Data Operations
Two register operations are provided: Register Write, and Register Read. In each case, the address of the affected register is
contained in the register pointer.
6.5.1
Register Write Command
The Register Write command format is shown in Table 20 . The least significant 8 bits of the Register Write command message
contain the data to be written to the register pointed to by the register pointer. The least significant 8 bits of the Register Write
response message contain the address of the register that was modified.
The write to the register is executed during the clock cycle immediately after CS is deasserted.
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
55
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